Title :
Fabrication technologies for three-dimensional integrated circuits
Author :
Reif, Rafael ; Fan, Andy ; Chen, Kuan-Neng ; Das, Shamik
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
Abstract :
The MIT approach to 3D VLSI integration is based on low-temperature Cu-Cu wafer bonding. Device wafers are bonded in a face-to-back manner, with short vertical vias and Cu-Cu pads as the inter-wafer throughway. In our scheme, there are several reliability criteria, which include: (a) structural integrity of the Cu-Cu bond; (b) Cu-Cu contact electrical characteristics; and (c) process flow efficiency and repeatability. In addition, CAD tools are needed to aid in design and layout of 3DICs. This paper discusses recent results in all these areas.
Keywords :
VLSI; circuit CAD; integrated circuit interconnections; integrated circuit manufacture; integrated circuit metallisation; integrated circuit reliability; interface structure; wafer bonding; 3D VLSI; 3D integrated circuits; 3DIC design; 3DIC layout; CAD tools; Cu; Cu-Cu bond structural integrity; Cu-Cu contact electrical characteristics; Cu-Cu pads; fabrication technologies; face-to-back bonded device wafers; inter-wafer throughway; low-temperature Cu-Cu wafer bonding; process flow efficiency; process flow repeatability; reliability criteria; short vertical vias; CMOS technology; Computer science; Epitaxial growth; Fabrication; Integrated circuit interconnections; Integrated circuit technology; Materials science and technology; System-on-a-chip; Three-dimensional integrated circuits; Wafer bonding;
Conference_Titel :
Quality Electronic Design, 2002. Proceedings. International Symposium on
Print_ISBN :
0-7695-1561-4
DOI :
10.1109/ISQED.2002.996687
