Title :
Using the Open Library Architecture (OLA) open source API in heterogeneous design flows
Author_Institution :
LSI Logic Inc., Bloomington, MN, USA
Abstract :
Design and timing closure are critical issues in modern design flows. Industry common library formats like .lib, CLF and TLF do not provide a means to embed arbitrary delay information and complex interconnect algorithms. Designers and silicon providers are at the mercy of these restrictions. Algorithms are applied to characterization data and proprietary interconnect analysis modules to minimize the error when mapping into these formats. The result is that numerous errors creep in to the tools that employ these formats. Often, these inaccuracies force unnecessary design iterations, technology guard banding, and finger pointing between the tool and library providers. With interconnect delay dominating path timing, it is more critical than ever to move past the text based library formats and to an API based solution that provides a way to embed interconnect analysis in the technology models. The Open Library Architecture addresses these issues by implementing an open C API. This API allows the library vendor to implement arbitrary data structures and algorithms. The same OLA module is employed consistently throughout the design flow which eliminates the loops which lead to inaccurate library mapping algorithms.
Keywords :
application program interfaces; circuit CAD; delays; electronic data interchange; integrated circuit design; integrated circuit interconnections; timing; OLA module; Open Library Architecture; Open Library Architecture open source API; arbitrary data structures; arbitrary delay information; characterization data; design closure; design flow; design iterations; embedded interconnect analysis; error minimization; heterogeneous design flows; industry common library formats; interconnect algorithms; interconnect delay; library format mapping; library mapping algorithms; open C API implementation; path timing; proprietary interconnect analysis modules; technology guard banding; technology models; text based library formats; timing closure; Algorithm design and analysis; Computer errors; Data structures; Databases; Delay; Electronic design automation and methodology; Large scale integration; Libraries; Signal analysis; Timing;
Conference_Titel :
Quality Electronic Design, 2002. Proceedings. International Symposium on
Print_ISBN :
0-7695-1561-4
DOI :
10.1109/ISQED.2002.996696