Chip level signal integrity analysis and crosstalk prediction using artificial neural nets

Recent ITRS predictions indicate that by the year 2011, the billion transistor monolithic die will be a reality. This clearly poses a challenge to gigascale integrated circuit design with regard to provision of multilevel interconnect wiring for the distribution of power, data and control signals to all parts of a chip. This paper addresses the problem of characterization, modeling and verification of 3D chip level interconnect crosstalk. The novel methodology proposed involves topological decomposition of interconnects into standard cells and the creation of parameterized models of these primitive structures using neural networks. Experimental results from a high performance operational amplifier demonstrates the viability of the approach.