Abstract :
Summary form only given. Embedded memories increasingly dominate SoC designs - whether chip area, performance, power consumption, manufacturing yield or design time are considered. ITRS data indicate that the embedded memory contents of ICs may increase from 20% in 1999 to 90% at the 50 nm node by the end of the decade. Therefore, even more than at present, the success of future SoC design will depend on the availability of high-quality embedded memories. Advanced process technologies pose new challenges for meeting these quality criteria. Some of the challenges are: providing flexible redundancy solutions for embedded SRAMs; designing competitive memories despite ever increasing leakage currents; reducing SRAM susceptibility to soft-error rate (SER). These challenges are bringing about the need for significant innovations in design of embedded memories, much more so than in recent previous process generations. In the presentation, the challenges are outlined and solutions are proposed. The focus of the discussion is on SRAM/ROM, but other technologies such as eDRAM and "1T SRAM" are also addressed.
Keywords :
DRAM chips; SRAM chips; embedded systems; integrated circuit design; integrated circuit reliability; integrated circuit yield; leakage currents; redundancy; technological forecasting; 1T SRAM; IC embedded memory content; ITRS data; ROM; SRAM; SRAM susceptibility; SoC; SoC designs; chip area; chip performance; chip power consumption; competitive memories; design time; eDRAM; embedded SRAM; embedded memories; flexible redundancy; leakage currents; manufacturing yield; process generations; process technologies; quality criteria; soft-error rate; Design automation; Energy consumption; Leakage current; Libraries; Manufacturing; Product design; Random access memory; Read only memory; Silicon; Technological innovation;
