DocumentCode :
2429196
Title :
Heat Transfer in a Three Dimensional Stacked Chip Scale Package (CSP) Module
Author :
Ragunathan, Srivathsan ; Goering, Douglas J. ; Karulkar, Pramod C.
Author_Institution :
Dept. of Mech. Eng., Alaska Univ., Fairbanks, AK
fYear :
2007
fDate :
18-22 March 2007
Firstpage :
244
Lastpage :
247
Abstract :
Stacking of chip scale packages (CSP) is a cost effective, manufacturable, and highly reliable approach to realizing a dense, high performance electronic system (Dewan-Sandur et al., 2006). However, system specific heat transfer and thermo-mechanical considerations severely limit the design and performance domain (Dewan-Sandur et al., 2006). Moreover, very limited generalized guidance on thermal design, except for the need to fully simulate the system, exists. This paper discusses thermal design of a forced-air cooled, eight level mu-BGA stacked CSP module and provides general guidelines as well as a non-dimensional formalism for analyzing cooling of such a 3D package. We have used a commercial CFD code (FLUENT) to analyze the steady-state thermal performance of an 8-level CSP module. The geometry is approximated by a 2D representation as the first step and is assumed to be made up of three solid layers, the polyimide tape, the elastomer adhesive and the silicon IC chip. The conjugate problem involving conduction in the solid layers and the forced convection due to air is solved by FLUENT. Temperature contours are produced for (a) power dissipation levels of 0.5, 1 and 1.5 W in the silicon chip, (b) silicon IC chip thicknesses of 50, 75 and 150 mum, (c) air gaps of 240, 320 and 400 mum and (d) air velocities of 3, 5 and 10 m/s. The effect of each of these parameters on the steady state temperature of the CSP is investigated. The results show that (1) a thicker silicon IC chip spreads heat laterally more effectively leading to more uniform temperatures along the chip, (2) the maximum temperature of the package in the center of the stack is directly proportional to the power level for a given silicon IC chip thickness and air velocity, (3) two Biot numbers (one based on the thickness of the silicon chip and the other based on the length) are identified to be crucial to the conduction along the chip and from the chip, and (4) the Nusselt number shows a dependence on th- e Graetz number akin to a hydrodynamically and thermally developing profile which motivates future work in this direction. Winged structures that increase the surface area for enhanced heat transfer surface are currently under active investigation.
Keywords :
ball grid arrays; chip scale packaging; cooling; 3D stacked chip scale package module; BGA; computational fluid dynamics; elastomer adhesive; heat transfer; nondimensional formalism; polyimide tape; silicon IC chip; steady state temperature; Chip scale packaging; Costs; Electronic packaging thermal management; Heat transfer; Manufacturing; Silicon; Solids; Stacking; Steady-state; Temperature dependence; Computational Fluid Dynamics (CFD); Stacked Chip Scale Package (CSP);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Thermal Measurement and Management Symposium, 2007. SEMI-THERM 2007. Twenty Third Annual IEEE
Conference_Location :
San Jose, CA
ISSN :
1065-2221
Print_ISBN :
1-4244-09589-4
Electronic_ISBN :
1065-2221
Type :
conf
DOI :
10.1109/STHERM.2007.352430
Filename :
4160918
Link To Document :
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