Ultra-low on-resistance LDMOS implementation in 0.13µm CD and BiCD process technologies for analog power IC´s

Author

Shirai, Koji ; Yonemura, Koji ; Watanabe, Kiminori ; Kimura, Koji

Author_Institution

Syst. LSI Div., Toshiba Semicond. Co., Yokohama, Japan

fYear

2009

fDate

14-18 June 2009

Firstpage

77

Lastpage

79

Abstract

Toshiba´s 5th generation BiCD/CD-0.13 is a new process platform for analog power applications based on 0.13 mum CMOS technology. The process platform has six varieties of rated voltage, 5V, 6V, 18V, 25V, 40V, and 60V. 5 to 18V CD-0.13 process use P-type silicon substrate. 25 to 60V BiCD-0.13 process use N-Epi wafer with N+/P+ buried layer on P type silicon substrate. Each LDMOS recode ultra-low on-resistance compared with that of previous papers, and we will realize the highest performance analog power IC´s using this technology.

Keywords

MOS integrated circuits; analogue integrated circuits; power integrated circuits; CMOS technology; analog power integrated circuits; process platform; ultra-low on-resistance LDMOS implementation; voltage 18 V; voltage 25 V; voltage 40 V; voltage 5 V; voltage 6 V; voltage 60 V; Power integrated circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on

Conference_Location

Barcelona

ISSN

1943-653X

Print_ISBN

978-1-4244-3525-8

Electronic_ISBN

1943-653X

Type

conf

DOI

10.1109/ISPSD.2009.5158005

Filename

5158005