Accumulation region length impact on 0.18µm CMOS fully-compatible lateral power MOSFETs with Shallow Trench Isolation

Author

Roig, J. ; Moens, P. ; Bauwens, F. ; Medjahed, D. ; Mouhoubi, S. ; Gassot, P.

Author_Institution

Power Technol. Centre - Corp. R&D, ON Semicond., Oudenaarde, Belgium

fYear

2009

fDate

14-18 June 2009

Firstpage

88

Lastpage

91

Abstract

N-type lateral power MOSFETs (nLDMOS) with shallow trench isolation (STI) and voltage capability between 12 and 22 V are analyzed in this work by experiment and TCAD simulation. A 0.18 mum CMOS technology is used to integrate nLDMOS devices without additional mask or process. Differently from previous works, the paramount impact of the accumulation region length (Lacc) on the safe operating area (SOA), gate-to-drain charge (Qgd) and hot carrier (HC) degradation is deeply explored to optimize the device electrical performance and reliability.

Keywords

CMOS integrated circuits; isolation technology; power MOSFET; power integrated circuits; CMOS technology; lateral power MOSFET; shallow trench isolation; voltage 12 V to 22 V; CMOS process; CMOS technology; Degradation; Hot carriers; Isolation technology; MOSFETs; Proximity effect; Research and development; Semiconductor optical amplifiers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on

Conference_Location

Barcelona

ISSN

1943-653X

Print_ISBN

978-1-4244-3525-8

Electronic_ISBN

1943-653X

Type

conf

DOI

10.1109/ISPSD.2009.5158008

Filename

5158008