Impact of inductance on timing characteristics of VLSI interconnects

Author

Servel, G. ; Huret, F. ; Paleczny, E. ; Kennis, P. ; Deschacht, D.

Author_Institution

CNRS, Montpellier, France

fYear

2000

fDate

2000

Abstract

As the result of the scaling down of technology and increased chip sizes, the cross-sectional area of wires has been reduced. With these trends, it is becoming crucial to be able to determine which nets within a high speed VLSI circuit exhibit prominent inductive effects. The object of this paper is to answer a question frequently put to designers: is inductance necessary to model interconnections or can a simple RC model be sufficient? By comparing the simulation results obtained from electrical simulations to an electromagnetic approach we can verify if the RC distributed model is always sufficient to characterize the propagation delay and the degradation due to the interconnect lines in submicronic circuit. Limits between RC and RLC models are determined

Keywords

VLSI; circuit simulation; delays; high-speed integrated circuits; inductance; integrated circuit interconnections; integrated circuit modelling; timing; EM simulations; RLC models; VLSI interconnects; cross-sectional area; electrical simulations; high speed VLSI circuit; inductance; propagation delay; timing characteristics; wires; Circuit simulation; Degradation; Electromagnetic modeling; Inductance; Integrated circuit interconnections; Propagation delay; RLC circuits; Timing; Very large scale integration; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Systems, 2000. Proceedings of the 2000 Third IEEE International Caracas Conference on

Conference_Location

Cancun

Print_ISBN

0-7803-5766-3

Type

conf

DOI

10.1109/ICCDCS.2000.869801

Filename

869801