Link switching: a communication architecture for configurable parallel systems

A novel class of interprocessor communication architectures for configurable systems is introduced. The communication network consists of switch elements connected in a simple, regular topology such as a ring or mesh, with multiple links running between them. Each processor element is connected to one switching element. Multiple links in conjunction with switching make it possible to realize other topologies, even those having higher connectivity. The network provides a bandwidth-connectivity tradeoff, i.e. greater connectivity can be achieved at the expense of lower bandwidth between adjacent nodes. A 1024-node, mesh-connected link switching architecture with 13 links of unit bandwidth between switching elements can be configured as a 10-D binary hypercube with unit bandwidth, a ten-level binary tree with bandwidth 6, or as a 9*9*9 mesh with bandwidth 4. The model unifies ideas from several previous architectures. Switches to implement this architecture have been designed and are being fabricated.<>