In search of the origin of VHDL´s delta delays

This paper has traced the VHDL architects´ journey into the world of delta delay including the original need for zero delay usage that evolved from a misconception that zero delays enhance simulation throughput without any penalty, the subsequent difficulties with the VHDL implementation of zero delay, the adapting of Conlan´s BCL model of time into VHDL as delta delay without a clear understanding of the consequences, and the problems that confront VHDL today. This paper has presented a simple solution to the problem that involves the elimination of zero delay usage and the specification of actual component delay values in terms of universal time.