Title :
Design of ESD protection device using statistical methods
Author :
Shigyo, N. ; Kawashima, H. ; Yasuda, S.
Author_Institution :
Syst. LSI Design Div., Toshiba Corp., Japan
Abstract :
This paper describes an ESD protection device design to minimize its area Ap while maintaining the breakdown voltage VESD. Hypothesis tests were performed to find the applied surge condition and to select control factors for the design-of-experiments (DOE). Also, TCAD was used to estimate VESD. An optimum device structure, where a salicide block was employed, was found using statistical methods and TCAD.
Keywords :
VLSI; design of experiments; electrostatic discharge; integrated circuit design; monolithic integrated circuits; protection; semiconductor device breakdown; technology CAD (electronics); DOE; ESD protection device design; TCAD; VLSI circuits; applied surge condition; breakdown voltage; control factors selection; design-of-experiments; optimum device structure; salicide block; statistical methods; Design methodology; Electrostatic discharge; Large scale integration; Performance evaluation; Protection; Statistical analysis; Testing; US Department of Energy; Variable structure systems; Very large scale integration;
Conference_Titel :
Quality Electronic Design, 2002. Proceedings. International Symposium on
Print_ISBN :
0-7695-1561-4
DOI :
10.1109/ISQED.2002.996769
