Real-time digit-serial decimating filter using systolic arrays and implemented in a CPLD

Author

Iparraguirre-Cárdenas, Daniel ; Santillan-Quinonez, Gerard F.

Author_Institution

Pontificia Univ. Catolica del Peru, Peru

fYear

2000

fDate

2000

Abstract

In this paper, a digit-serial decimating filter using a systolic architecture is presented for digit-sizes 1, 2 and 4. The flip-flop´s clock enable inputs are used for the multipliers to work at half the clock frequency, so it is possible for the filter to work at a higher frequency than the apparent result of the timing simulation. The CPLD features are used to increase the clock frequency, as well as the different synthesis options. This design has a real-time computing capability. The architecture has been designed with Max+Plus II 9.01 and simulated using FLEX 10 K devices of the Altera family

Keywords

digital filters; programmable logic devices; real-time systems; systolic arrays; Altera family; CPLD; FLEX 10 K devices; Max+Plus II 9.01; clock frequency; digit-serial decimating filter; flip-flops; multipliers; real-time computing capability; systolic architecture; systolic arrays; Arithmetic; Clocks; Computational modeling; Computer architecture; Data processing; Filtering; Filters; Frequency; Logic arrays; Systolic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Systems, 2000. Proceedings of the 2000 Third IEEE International Caracas Conference on

Conference_Location

Cancun

Print_ISBN

0-7803-5766-3

Type

conf

DOI

10.1109/ICCDCS.2000.869812

Filename

869812