Title :
Design trade-offs in SHA-3 multi-message hashing on FPGAs
Author :
Ayuzawa, Yusuke ; Fujieda, Naoki ; Ichikawa, Shuichi
Author_Institution :
Dept. of Electr. & Electron. Inf. Eng., Toyohashi Univ. of Technol., Toyohashi, Japan
Abstract :
Hash functions are widely used to check whether the data are correctly transferred. Keccak is an important hash function that was selected as SHA-3 in 2012. In this paper, we propose and evaluate the optimized FPGA implementations of Keccak for multi-message hashing. Our optimizations include a variety of pipeline organizations, retiming of a part of the calculation, and the use of DSP units. According to the evaluation results, our implementation exhibited 52% higher throughput/area than the previous one on a Xilinx Virtex-5 FPGA. Although the above design adopted advanced DSP units that support bitwise XOR, 20% improvement was achieved even on a Spartan-6 with simpler multiply-adders.
Keywords :
cryptography; field programmable gate arrays; DSP units; Keccak hash function; SHA-3 multimessage hashing; Spartan-6; Xilinx Virtex-5 FPGA; bitwise XOR; design trade-off; digital signal processor; field programmable gate array; multiply-adders; Digital signal processing; Field programmable gate arrays; Optimization; Pipeline processing; Pipelines; Table lookup; Throughput;
Conference_Titel :
TENCON 2014 - 2014 IEEE Region 10 Conference
Conference_Location :
Bangkok
Print_ISBN :
978-1-4799-4076-9
DOI :
10.1109/TENCON.2014.7022311