DocumentCode
2429824
Title
A novel BIST approach for testing logic resources using Hard Macro
Author
Zhang, Zhiquan ; Wen, Zhiping ; Chen, Lei ; Zhang, Fan ; Zhou, Tao
Author_Institution
Beijing Microelectron. Tech.Instn., Beijing
fYear
2008
fDate
7-11 June 2008
Firstpage
379
Lastpage
381
Abstract
This paper explores an new Built-In Self-Test (BIST) approach to test the configurable logic blocks (CLBs) of Xilinx Virtex FPGAs using Hard Macro. The proposed approach completely detects and diagnoses single and multiple stuck-at gate-level faults as well as associated signal lines in the CLBs, while significantly reducing the Outputs needed to be compared by ORAs. Only 24 total test configurations for two sessions are required while retrieving the BIST results using scan chain method.
Keywords
built-in self test; fault diagnosis; field programmable gate arrays; logic testing; BIST approach; Xilinx Virtex FPGA; built-in self-test; configurable logic blocks; hard macro; logic testing; scan chain method; stuck-at gate-level faults; Built-in self-test; Circuit faults; Fault detection; Field programmable gate arrays; Hardware design languages; Logic testing; Microelectronics; Neural networks; Reconfigurable logic; Signal processing; BIST; FPGA Testing; Hard Macro;
fLanguage
English
Publisher
ieee
Conference_Titel
Neural Networks and Signal Processing, 2008 International Conference on
Conference_Location
Nanjing
Print_ISBN
978-1-4244-2310-1
Electronic_ISBN
978-1-4244-2311-8
Type
conf
DOI
10.1109/ICNNSP.2008.4590376
Filename
4590376
Link To Document