Time and spatial resolved measurement and control of temperature in integrated MOS-power devices

A method for the time and spatial resolved temperature measurement during active operation of large area integrated LDMOS transistors will be presented. The method uses the temperature dependence of the resistance of the transistors polysilicon gate network and refers to LDMOS transistors realized in 0.18 mue HV-CMOS-technology. A spatial resolved measurement over the surface of the device will be reached by a segmented arrangement of multiple gate contacts to the gate electrode network. The segmented contacting scheme can also be used for an independent control of the different device segments and in such way for the control of the dissipated power and temperature development in the respective segments.