A new model for aluminum interconnect fusing caused by ESD

Electrical Overstress (EOS) in semiconductor devices accounts for a large number of the failures that occur in both the vendor´s facility as well as in the field. Improvements in the circuit design and layout require techniques that accurately model this damage. This paper provides the details necessary to model fusing of aluminum interconnect caused by electrostatic discharge. It also highlights the important material properties necessary to improve a circuit´s response to EOS or ESD events