DocumentCode
2429917
Title
Improved performance second order time delay digital tanlock loop
Author
Al-Araji, S.R. ; Al-Ali, O. A Al-Kharji ; Al-Qutayri, M.A. ; Anani, N.A. ; Ponnapalli, P.
Author_Institution
Coll. of Eng., Khalifa Univ. of Sci., Technol. & Res., Sharjah, United Arab Emirates
fYear
2010
fDate
12-14 April 2010
Firstpage
1
Lastpage
5
Abstract
This paper presents a second order time delay digital tanlock loop with improved locking as well as acquisition performance. The former is achieved through replacement of the delay unit of the TDTL by a variable one whose phase error is controlled by the output of the phase detector. This approach maintains the quadrature relationship between the two TDTL channels and hence results in a linearized phase detector characteristics. Fast acquisition is obtained through modification of the free running sampling frequency of digital controlled oscillator (DCO) in order to speed up the loop digital filter response. This improved architecture was tested using various input signals including FSK (frequency shift keying) and the results show an enhanced performance when compared with the original TDTL system.
Keywords
data acquisition; digital filters; digital phase locked loops; frequency shift keying; oscillators; phase detectors; acquisition performance; delay unit; digital controlled oscillator; free running sampling frequency; frequency shift keying; input signals; linearized phase detector characteristics; loop digital filter response; phase error; quadrature relationship; second order time delay digital tanlock loop; Delay effects; Detectors; Digital control; Digital filters; Digital-controlled oscillators; Error correction; Frequency shift keying; Phase detection; Sampling methods; System testing; FSK; PLL; TDTL; acquisition; lock range;
fLanguage
English
Publisher
ieee
Conference_Titel
Sarnoff Symposium, 2010 IEEE
Conference_Location
Princeton, NJ
Print_ISBN
978-1-4244-5592-8
Type
conf
DOI
10.1109/SARNOF.2010.5469790
Filename
5469790
Link To Document