Interconnect failure due to voltage and humidity in a 30V BCD technology

This paper describes a failure mechanism that caused open-circuit failures in the interconnect layers of several ICs fabricated in a 30 V Bipolar-CMOS-DMOS (BCD) technology under highly-accelerated stress testing (HAST). A detailed failure analysis is presented, showing that there were several contributing factors to this failure mechanism, including top metal thickness, passivation stress, package-induced stress, interconnect voltage, and humidity.