Title :
Interconnect failure due to voltage and humidity in a 30V BCD technology
Author :
Disney, Don ; Blattner, Robert
Author_Institution :
Adv. Analogic Technol., Inc., Santa Clara, CA, USA
Abstract :
This paper describes a failure mechanism that caused open-circuit failures in the interconnect layers of several ICs fabricated in a 30 V Bipolar-CMOS-DMOS (BCD) technology under highly-accelerated stress testing (HAST). A detailed failure analysis is presented, showing that there were several contributing factors to this failure mechanism, including top metal thickness, passivation stress, package-induced stress, interconnect voltage, and humidity.
Keywords :
BIMOS integrated circuits; integrated circuit interconnections; bipolar-CMOS-DMOS technology; highly-accelerated stress testing; interconnect layers; open-circuit failures; voltage 30 V; Failure analysis; Humidity; Integrated circuit testing; Metallization; Passivation; Product design; Qualifications; Stress; Temperature; Voltage;
Conference_Titel :
Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on
Conference_Location :
Barcelona
Print_ISBN :
978-1-4244-3525-8
Electronic_ISBN :
1943-653X
DOI :
10.1109/ISPSD.2009.5158039
