ESD protection structure with novel trigger technique for LDMOS based on BiCD process

This paper presents ESD protection structure with novel trigger technique for LDMOS based on BiCD process. The proposed ESD protection element includes the same structure as drain region in Nch-LDMOS, the vertical NPN transistor and the lateral NPN transistor. The trigger voltage is depended on the breakdown voltage in the drain region integrated in ESD protection device and the avalanche current acts as the base current of NPN transistor. The high ESD current spreads to the buried layer in the vertical NPN transistor without locally concentrating in the drain edge. The value of the second breakdown trigger current It2 in the proposed ESD protection element is nearly four times as large as that in the simple LDMOS.