aBCD18 - An advanced 0.18um BCD technology for PMIC application

Author

Park, Namkyu ; Cha, Jaehan ; Lee, Kyungho ; Jeon, Haeung ; Choi, Hyungsuk ; Kim, Juho ; Kim, Sungoo ; Oh, Inseok ; Park, Eungryul ; Chae, Jinyoung ; Kang, Hyunggeun ; Oh, Intaek ; Sub Yoon, Han

Author_Institution

SMS Div., Magnachip, Cheongju, South Korea

fYear

2009

fDate

14-18 June 2009

Firstpage

231

Lastpage

234

Abstract

We present a new advanced 0.18 um BCD(Bipolar-CMOS-DMOS) technology with the key features being a 40 V HV-MOS and an SSTC(Sidewall Selective Transistor Cell) type EEPROM as well as complimentary available analog devices such as a high gain BJT, 4fF/um² MIM capacitor, and 10k Omega/sq. poly resistor. To reduce device area and enhance latch up immunity, a 15 um depth deep trench isolation process has been developed, which will help to significantly reduce the chip size.

Keywords

BIMOS integrated circuits; EPROM; MIM devices; capacitors; isolation technology; power integrated circuits; resistors; EEPROM; MIM capacitor; analog devices; bipolar-CMOS-DMOS technology; deep trench isolation process; depth 15 mum; poly resistor; sidewall selective transistor; size 0.18 mum; Auditory displays; Diffusion tensor imaging; EPROM; Isolation technology; Logic devices; MIM capacitors; Metal-insulator structures; Nonvolatile memory; Resistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on

Conference_Location

Barcelona

ISSN

1943-653X

Print_ISBN

978-1-4244-3525-8

Electronic_ISBN

1943-653X

Type

conf

DOI

10.1109/ISPSD.2009.5158044

Filename

5158044