DocumentCode :
2430079
Title :
An array-based scalable architecture for DCT computations in video coding
Author :
Huang, Jian ; Lee, Jooheung ; Ge, Yimin
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Univ. of Central Florida, Orlando, FL
fYear :
2008
fDate :
7-11 June 2008
Firstpage :
451
Lastpage :
455
Abstract :
In this paper, we propose an array-based architecture for DCT computation with high scalability. The scalable architecture can perform DCT computations for 15 different zones and 8 different precisions to achieve quality scalability for DCT coefficients. Due to the quantization process in video coding, the quality can still be retained for larger quantization parameter. We show the detailed comparisons between the quality scalability and the tradeoff factors, i.e., throughput, hardware resources, clock frequencies, and power consumptions.
Keywords :
discrete cosine transforms; power consumption; quantisation (signal); video coding; DCT computations; array-based architecture; clock frequencies; discrete cosine transform; hardware resources; power consumptions; quality scalability; quantization process; scalable architecture; video coding; Clocks; Computer architecture; Discrete cosine transforms; Energy consumption; Frequency; Hardware; Quantization; Scalability; Throughput; Video coding; DCT; FPGA; Video Coding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Neural Networks and Signal Processing, 2008 International Conference on
Conference_Location :
Nanjing
Print_ISBN :
978-1-4244-2310-1
Electronic_ISBN :
978-1-4244-2311-8
Type :
conf
DOI :
10.1109/ICNNSP.2008.4590391
Filename :
4590391
Link To Document :
بازگشت