Scaling of vertical and lateral MOSFETs in the deep submicrometer range

Conventional lateral and vertical n-channel MOS transistors with channel length in the range of 350 nm to 40 nm have been systematically investigated by means of device simulation. In principle, vertical MOSFETs with different layer designs show a similar DC behaviour to conventional lateral devices. The vertical planar doped barrier MOSFET (PDBFET) exhibits the highest transconductance already for longer channel length. On the other hand, caused by the large gate contact overlap to source/drain layers, the different vertical transistor versions show only low values of the cutoff frequency compared to lateral devices. The reduction of this overlap and an increase of the oxide thickness between the gate contact and the substrate material can considerably improve the small signal behaviour of vertical MOS transistors. For example, for optimized vertical homogeneously doped transistors with 130 nm channel length cut off frequencies of over 65 GHz have been predicted at V_ds=2.0 V