Impact of an LPT(II) concept with Thin Wafer Process Technology for IGBT´s vertical structure

In this paper, for the first time, 600 ~ 6500 V IGBTs utilizing a new vertical structure of ldquoLight Punch-Through (LPT) (II)rdquo with Thin Wafer Process Technology demonstrate high total performance with low overall loss and high safety operating area (SOA) capability. This collector structure enables a wide position in the trade-off characteristics between on-state voltage (V_CE(sat)) and turn-off loss (E_OFF) without utilizing any conventional carrier lifetime technique. In addition, this device concept achieves a wide operating junction temperature (@218 ~ 423 K) of IGBT without the snap-back phenomena (les298 K) and thermal destruction (ges398 K). From the viewpoint of the high performance of IGBT, the breaking limitation of any Si wafer size, the proposed LPT(II) concept that utilizes an FZ silicon wafer and Thin Wafer Technology is the most promising candidate as a vertical structure of IGBT for the any voltage class.