Design of Double Gate MOSFET and FDSOI using high k material for nano scaled Circuits

The rapid technology developments in the metal-oxide-semiconductor industry have lead to CMOS scaling down to the sub-20nm regime, and according to the 2009 ITRS projections printed gate lengths will scale down to approximately 12nm by 2020, resulting in significant changes in both the information processing technology as well as the device manufacturing technology. The most promising devices now a days are DG-MOSFET and FDSOI-MOSFET. In this paper downscaling design and simulation of NMOS transistor with 18nm gate length considered. A hafnium oxide (HfO₂) is used as the high k material instead of SiO₂ with Al metal gate. The LDDG (Lightly Doped Double Gate) MOSFET and FDSOI NMOS transistor and electrical characteristics is simulated using GENIUS simulator. A simulation results optimal values of threshold voltage (Vth), Leakage currents and ION/IOFF ratio. The ION/IOFF of DG-MOSFET is 3.4 times greater than the FDSOI.