Title :
Overlapped subarray testing for wafer scale integration
Author :
Malek, Miroslaw ; Swartzlander, Earl E., Jr.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
A testing technique for wafer-scale integration arrays is introduced. It guarantees a high-fault coverage without specific requirements on design for testability. The technique is based on overlapped subarray testing and is capable of covering the vast majority of fault types including pattern sensitivity. Formulas giving the number of subarrays that must be tested for arbitrary array and partition sizes are derived. An example of testing a VLSI multiplier (which demonstrated pattern sensitivity faults) is given
Keywords :
VLSI; integrated circuit testing; multiplying circuits; VLSI multiplier; fault coverage; overlapped subarray testing; partition sizes; pattern sensitivity; testability; wafer scale integration; Circuit faults; Circuit testing; Computer aided manufacturing; Design for testability; Logic testing; Manufacturing processes; Partitioning algorithms; System testing; Very large scale integration; Wafer scale integration;
Conference_Titel :
Wafer Scale Integration, 1989. Proceedings., [1st] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-9901-9
DOI :
10.1109/WAFER.1989.47564
