Notice of Violation of IEEE Publication PrinciplesA wideband LNA design based on body bias suitable for low voltage and low power application

Notice of Violation of IEEE Publication Principles

"A Wideband LNA Design Based on Body Bias Suitable for Low Voltage and Low Power Application"
by Sunil Kumar Pandey, Sachin Agrawal, Jawar Singh and Manoj S. Parihar
in the Proceedings of the IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), January 2014

After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE\´s Publication Principles.

This paper copied large sections of text and figures from the paper cited below. The original content was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission. The lead author, Sunil Kumar Pandey, was responsible for the misconduct, and the coauthors were unaware of the paper.

"A New Technique for Broadwidth Enhancement of Low Voltage Current Mirror"
by Vandana Niranjan, Ashwani Kumar, Shail Bala Jain
Submitted to the International Conference on Control, Automation, Robotics and Embedded Systems (CARE) submitted 7 November 2013

A wideband low noise amplifier (LNA) based on body bias technique suitable for low voltage and low power application is presented. Total transconductance of MOS transistor is increased by using body bias technique. Forward body bias (FBB) technique reduces V_th and it solves the problem of low voltage design. In designing LNA, the main concerns are high gain and low noise figure with small return loss. The reported LNA exhibits the best noise and gain performance when compared with existing circuits. The proposed LNA operates in wideband (1-11 GHz) and dissipates power of 19.3 mW from 0.75V supply voltage. The power gain S21, noise figure (NF), input and output reflection coefficients are 10-32 dB, 0.1-1.5 dB, S11 <;-10 dB and S22 <;-15 dB, respectively. A st- ndard 90 nm CMOS process is used for simulation.