High-Performance Computing Based on Heterogeneous and Reconfigurable Architectures

Author

Sousa, Éricles Rodrigues ; Meloni, Luís Geraldo Pedroso

Author_Institution

Sch. of Electr. & Comput. Eng., State Univ. of Campinas - UNICAMP, Campinas, Brazil

fYear

2012

fDate

3-5 Nov. 2012

Firstpage

530

Lastpage

534

Abstract

This paper aims to describe a proposal of a reconfigurable and heterogeneous computing architecture for digital signal processing on embedded systems, based on the cooperative code execution between DSP (Digital Signal Processor) and FPGAs (Field-Programmable Gate Arrays). In order to validate this approach, some scenarios has been developed for processing using FFT (Fast Fourier Transform) and DCT (Discrete Cosine Transform) algorithm, which has been one of the main module used for digital image compression and also is applied in several coding schemes, such as JPEG, MPEGx and H.26x.

Keywords

digital signal processing chips; discrete cosine transforms; embedded systems; fast Fourier transforms; field programmable gate arrays; parallel processing; reconfigurable architectures; DCT algorithm; DSP; FFT; FPGA; H.26x; JPEG; MPEGx; coding scheme; cooperative code execution; digital image compression; digital signal processing; digital signal processor; discrete cosine transform; embedded system; fast Fourier transform; field-programmable gate array; heterogeneous computing architecture; high-performance computing; reconfigurable computing architecture; Computer architecture; Digital signal processing; Discrete cosine transforms; Field programmable gate arrays; Hardware; Signal processing algorithms; Software; DSP; Embedded Systems; FPGA; High Performance Computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computational Intelligence and Communication Networks (CICN), 2012 Fourth International Conference on

Conference_Location

Mathura

Print_ISBN

978-1-4673-2981-1

Type

conf

DOI

10.1109/CICN.2012.125

Filename

6375170