A Methodical Approach to Hybrid PLL Design for High-Speed Wireless Communications

Coherent demodulation in digital wireless communications involves generating a local carrier that is in phase with the received carrier, and then using this local carrier in order to coherently demodulate the received signal. Generation of the local carrier is done via a carrier synchronization phase lock loop (PLL). The receiver also includes a symbol timing synchronization PLL, whose purpose is to determine the optimal times for sampling of the recovered symbol waveforms. PLLs are either: (i) analog; (ii) digital; or (iii) hybrid. In this paper we develop a methodical approach for the application of digital signal processing theory to the design and implementation of hybrid PLLs used in coherent receivers. The methodological nature of our approach will manifest itself in the development of a clear step-by-step procedure for the design of the constituent components of the hybrid PLL. This procedure will explicitly address various aspects and difficulties unique to hybrid implementations