• DocumentCode
    2431461
  • Title

    Refinement and reuse of TLM 2.0 models: The key for ESL success

  • Author

    Reyes, Victor

  • Author_Institution
    NXP Semicond., Eindhoven, Netherlands
  • fYear
    2009
  • fDate
    28-30 April 2009
  • Firstpage
    102
  • Lastpage
    105
  • Abstract
    ESL design methods and tools are being proposed to improve the productivity of the designers and to bridge the design and verification gaps. The main area where ESL solutions are being successfully applied on current desire flows is virtual prototyping. The success of these methods relies on the rapidly adoption from semiconductor industry and EDA vendors of standards such as SystemC and TLM 2.0. Ideally. TLM models must be accurate enough, fast enough and easy to create in order to fit all virtual prototype use-cases. However reality shows that different requirements are achieved only by using different type of models (the right model for the right use-case). This is because TLM modeling is a multidimensional problem where the different dimensions (speed, timing accuracy and modeling effort) are orthogonal with each other. Having to create and maintain a separated model for each use-case is drastically reducing the benefits of VP technology, due to elevated cost of creating and maintaining the models consistent with each other. Therefore, model reuse and refinement is a must for the success of ESL technology. This paper describes modeling concepts that can be used to create speed optimal models with low effort, which can be gradually refined with more timing accuracy and therefore reused for different VP use-cases.
  • Keywords
    circuit CAD; semiconductor device models; semiconductor industry; virtual prototyping; ESL design methods; SystemC; TLM 2.0 models; multidimensional problem; semiconductor industry; virtual prototyping; Accuracy; Bridges; Costs; Design methodology; Electronic design automation and methodology; Electronics industry; Multidimensional systems; Productivity; Timing; Virtual prototyping;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on
  • Conference_Location
    Hsinchu
  • Print_ISBN
    978-1-4244-2781-9
  • Electronic_ISBN
    978-1-4244-2782-6
  • Type

    conf

  • DOI
    10.1109/VDAT.2009.5158105
  • Filename
    5158105