Title :
Circuit acyclic clustering with input/output constraints and applications
Author :
Lin, Rung-Bin ; Lin, Tsung-Han ; Wu, Shin-An
Author_Institution :
Comput. Sci. & Eng., Yuan Ze Univ., Chungli, Taiwan
Abstract :
This article studies a new circuit acyclic clustering problem which divides a combinational circuit into groups of sub-circuits, each of which has limited numbers of inputs and outputs. Several heuristics are proposed to solving this problem. We achieve 300% speedup on logic simulation, with an application of our approach, for finding an input vector that incurs minimum or maximum leakage power dissipation.
Keywords :
circuit simulation; combinational circuits; logic design; circuit acyclic clustering; combinational circuit i; input-output constraint; logic simulation; Application software; Circuit simulation; Clustering algorithms; Combinational circuits; Computer science; Flip-flops; Latches; Logic circuits; Logic gates; Power dissipation;
Conference_Titel :
VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-2781-9
Electronic_ISBN :
978-1-4244-2782-6
DOI :
10.1109/VDAT.2009.5158107