Title :
Multiscale modeling in semiconductor processing
Author_Institution :
NASA Ames Res. Center, Moffett Field, CA, USA
Abstract :
Process modeling in semiconductor device fabrication has become an accepted practice in the industry and commercial codes are available to model diffusion, ion implantation, dopant segregation and a variety of other processes. There is a certain level of empiricism associated with each of these models. This leads to the need where the empirical part of the model has to be constantly re-evaluated as processing goes through new generations. On the other hand, if completely self consistent, first-principles based models can be developed, it would be applicable through several generations of device technologies. In this paper, we attempt such an approach for one process: trench etching, gate definition and associated etching processes.
Keywords :
etching; semiconductor process modelling; gate definition; multiscale modeling; semiconductor processing; trench etching; Etching; Fabrication; Inductors; NASA; Plasma applications; Plasma chemistry; Plasma simulation; Poisson equations; Semiconductor devices; Semiconductor process modeling;
Conference_Titel :
Computational Electronics, 2000. Book of Abstracts. IWCE Glasgow 2000. 7th International Workshop on
Conference_Location :
Glasgow, UK
Print_ISBN :
0-85261-704-6
DOI :
10.1109/IWCE.2000.869915