Area efficient processing element architecture for compact hash functions systems on VIRTEX5 FPGA platform

This paper presents the design and analysis of an area efficient processing element structure for use in cryptographic systems especially for implementing hash functions. The proposed architecture achieves significant efficiency improvements based on a reduction in area. We demonstrate a compact processing element on FPGA. As a proof of concept, we employed that compact processing element in the implementation of the Blue Midnight Wish (BMW) hash function which is one of the fastest candidates in the 2nd round SHA-3 hash function competition when implemented in software. With our new processing element, on Xilinx Virtex-5 we implemented BMW-256 in just 51 slices achieving a throughput of 68.71 Mbps and BMW-512 in just 105 slices achieving a throughput of 112.18 Mbps. Our design of the new processing element (PE) require the use of block RAM memory for storing the internal structure of the hash functions as well as for the PE instruction logic.