Title :
Logic synthesis for better than worst-case designs
Author :
Cong, Jason ; Minkovich, Kirill
Author_Institution :
Comput. Sci. Dept., Univ. of California, Los Angeles, CA, USA
Abstract :
In this paper we present a novel metric for measuring and optimizing the performance of circuits that operate with the clock period smaller than the worst-case delay. In particular, we developed an efficient logic optimization operation ldquobalancerdquo and a library mapping algorithm named BTWLibMap. Together they are able to reduce the probability of a timing error by 2.3X while only incurring a 4% area overhead.
Keywords :
circuit optimisation; logic design; BTWLibMap; clock period; library mapping algorithm; logic optimization operation; logic synthesis; timing error; worst-case delay; Circuit optimization; Clocks; Delay; Design optimization; Latches; Logic circuits; Logic design; Pipelines; Registers; Timing;
Conference_Titel :
VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-2781-9
Electronic_ISBN :
978-1-4244-2782-6
DOI :
10.1109/VDAT.2009.5158121
