DocumentCode :
2431845
Title :
An All-Digital Clock Recovery Architecture for the BRAN Hiperaccess Uplink Receiver
Author :
Savazzi, Pietro ; Gamba, Paolo ; Callegari, Sergio
Author_Institution :
Dipt. di Elettronica, Pavia Univ.
Volume :
5
fYear :
2006
fDate :
7-10 May 2006
Firstpage :
2206
Lastpage :
2210
Abstract :
In this work, an all-digital synchronization recovery circuit is proposed for the uplink scheme of the ETSI BRAN Hiperaccess receiver. In particular a fast, open-loop algorithm, which exploits the TDMA burst preamble made of 16 or 32 cazac symbols, is tested by means of a link-level simulator operating at twice the symbol rate. At the receiver we suppose to use a fixed local oscillator and the symbol timing recovery is performed by means of digital interpolation. The fractional delay parameter for a fourth and sixth order Farrow interpolator is computed by means of a second order polynomial representation of the maximum likelihood function. After the recovery of the symbol timing, the phase offset is adjusted by simply taking the argument of the log-likelihood function. Performances of the proposed architecture are evaluated by measuring the symbol error rate and the synchronization error variances on AWGN channel
Keywords :
AWGN channels; interpolation; maximum likelihood estimation; polynomial approximation; radio access networks; radio links; radio receivers; synchronisation; time division multiple access; AWGN channel; BRAN Hiperaccess uplink receiver; ETSI BRAN Hiperaccess receiver; Farrow interpolator; TDMA burst; additive white Gaussian noise channel; all-digital clock recovery architecture; all-digital synchronization recovery circuit; digital interpolation; fixed local oscillator; fractional delay parameter; log-likelihood function; maximum likelihood function; phase offset; second order polynomial representation; symbol error rate; symbol timing recovery; synchronization error variances; time division multiple access; Circuit simulation; Circuit testing; Clocks; Computational modeling; Interpolation; Local oscillators; Synchronization; Telecommunication standards; Time division multiple access; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Vehicular Technology Conference, 2006. VTC 2006-Spring. IEEE 63rd
Conference_Location :
Melbourne, Vic.
ISSN :
1550-2252
Print_ISBN :
0-7803-9391-0
Electronic_ISBN :
1550-2252
Type :
conf
DOI :
10.1109/VETECS.2006.1683248
Filename :
1683248
Link To Document :
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