Hybrid CMOS/nanodevice circuits for high throughput pattern matching applications

We propose a class of novel hybrid CMOS/nanodevice circuits for pattern matching applications (e.g. real-time network intrusion detection, network packet routing, DNA sequencing), with the potential for dramatic improvements in throughput, density, and power performance relative to state-of-the-art designs. The performance advantage of our novel circuits is mainly due to three factors: the implementation of a ternary content addressable memory cell with stackable ultra-dense resistive switching (“memristive” or RRAM) devices; three dimensional hybrid CMOS/nanodevice circuitry with an area-distributed interface enabling high communication bandwidth between the memory and CMOS subsystems; and use of a modified CMOL FPGA fabric with low reconfiguration overhead.