Title :
Process and characterization of Strained Silicon MOSFET incorporating Dielectric Pocket (SDP-MOSFET)
Author :
Napiah, Zul Atfyi Fauzan Mohammed ; Idris, Muhammad Idzdihar ; Said, Muzalifah Mohd ; Hamid, Afifah Maheran Abdul ; Ali, Nur Alisa ; Hamzah, Rostam Affendi
Author_Institution :
Fac. of Electron. & Comput. Eng., Univ. Teknikal Malaysia Melaka, Durian Tunggal, Malaysia
Abstract :
In this paper, we propose a fabrication process of Strained Silicon MOSFET incorporating Dielectric Pocket (SDP-MOSFET). By employing TCAD tools, a systematic process simulation in realizing the SDP-MOSFET structure is done successfully. By using vertical and horizontal doping profiles, 120 nm gate length with 12 nm gate oxide of the device is observed respectively. The combination of a Silicon Germanium (SiGe) layer and incorporation of dielectric pocket (DP) shows an improved in suppression of short channel effects (SCE) and allows the threshold voltage and the performance of the devices to be optimized. A low leakage current (IOFF), good drive current (ION), higher mobility and lower power consumption are obtained in SDP-MOSFET. Consequently, the threshold voltage (VT) is decreased accordingly in SDP-MOSFET devices and shows a better control of VT roll-off.
Keywords :
Ge-Si alloys; MOSFET; elemental semiconductors; semiconductor doping; silicon; technology CAD (electronics); SCE; SDP-MOSFET devices; SiGe; TCAD tools; fabrication process; gate oxide; horizontal doping profiles; metal-oxide-semiconductor field effect transistor; power consumption; short channel effects; silicon germanium layer; size 12 nm; size 120 nm; strained silicon MOSFET incorporating dielectric pocket; systematic process simulation; vertical doping profiles; Dielectrics; Doping; Logic gates; MOSFET circuits; Silicon; Silicon germanium; Strain;
Conference_Titel :
Micro and Nanoelectronics (RSM), 2011 IEEE Regional Symposium on
Conference_Location :
Kota Kinabalu
Print_ISBN :
978-1-61284-844-0
DOI :
10.1109/RSM.2011.6088286
