A frequency synthesizer for Mode-1 MB-OFDM UWB applications

Author

Chang, Jung-Yu ; Fan, Che-Wei ; Liu, Shen-Iuan

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2009

fDate

28-30 April 2009

Firstpage

219

Lastpage

222

Abstract

A frequency synthesizer for Mode-1 MB-OFDM UWB applications is realized in 65 nm CMOS. By using a delay-locked loop (DLL) and the proposed multiply-by-two circuit, the frequency synthesizer achieves the in-band spur of -40 dBc for the three-band operation. The proposed multiply-by-2 circuit realizes the quadrature signals, and its input signals do not need the 50% duty cycle. A modified current-starving cell in a DLL is also proposed to reduce the supply noise sensitivity. The measured switching time from 3.342 GHz to 4.488 GHz is around 1.1 ns. The area is 1.25times1.175 mm² with pads and the power is 19.2 mW for 1.2 V supply.

Keywords

CMOS digital integrated circuits; OFDM modulation; delay lock loops; field effect MMIC; frequency synthesizers; ultra wideband communication; CMOS process; Mode-1 MB-OFDM; UWB applications; delay-locked loop; frequency 3.342 GHz to 4.488 GHz; frequency synthesizer; multiply-by-two circuit; noise sensitivity reduction; power 19.2 mW; quadrature signals; size 65 nm; switching time measurement; time 1.1 ns; voltage 1.2 V; Amplitude modulation; Circuits; Clocks; Delay; Frequency conversion; Frequency synthesizers; Phase frequency detector; Phase locked loops; Phase noise; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on

Conference_Location

Hsinchu

Print_ISBN

978-1-4244-2781-9

Electronic_ISBN

978-1-4244-2782-6

Type

conf

DOI

10.1109/VDAT.2009.5158134

Filename

5158134