An 18.7mW 10-GHz Phase-Locked Loop Circuit in 0.13-µm CMOS

Author

Tseng, I-Wei ; Wu, Jen-Ming

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2009

fDate

28-30 April 2009

Firstpage

227

Lastpage

230

Abstract

This paper presents a 10-GHz phase-locked loop (PLL) design with low power for high speed networking. A mixed design of current mode logic (CML) and true single phase clock (TSPC) logic is presented to reduce the power consumption of the frequency divider. With gain-boosting design in the charge pump leads to low jitter and low reference spur. An additional diversity of VCO by user body bias is proposed to improve KVCO. The PLL circuit is fabricated in TSMC 0.13mum RF CMOS process. The chip occupies 1.03 times 0.91 mm², draws less than 18.7mW from a 1.2V supply, and is -117.43dBc/Hz at an offset frequency of 1MHz from the carrier.

Keywords

CMOS integrated circuits; current-mode logic; frequency dividers; phase locked loops; voltage-controlled oscillators; CMOS; VCO; current mode logic; frequency 10 GHz; frequency divider; gain-boosting design; high speed networking; phase-locked loop circuit; power 18.7 mW; power consumption reduction; size 0.13 mum; true single phase clock logic; voltage 1.2 V; CMOS logic circuits; Charge pumps; Clocks; Energy consumption; Frequency conversion; High-speed networks; Jitter; Logic design; Phase locked loops; Voltage-controlled oscillators; Phase-Locked Loop (PLL); True Single Phase Clock (TSPC); current mode logic (CML); frequency divider; gain boosting;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on

Conference_Location

Hsinchu

Print_ISBN

978-1-4244-2781-9

Electronic_ISBN

978-1-4244-2782-6

Type

conf

DOI

10.1109/VDAT.2009.5158136

Filename

5158136