Field effect in silicon nanostructure fabricated by Atomic Force Microscopy nano lithography

The electrical property of silicon nano-structure is highly considered in nanoelectronics. In this context we investigate the field effect in nanostructure Junctionless p-type silicon nanowire transistor under the lateral gate voltage. The device fabricated by means of Atomic Force microscopy (AFM) nano lithography on Silicon on Insulator (SOI) wafer. I-V characteristic and the Drain/Source current under the lateral gate voltage investigated. The subthreshold swing measured and hysteresis effect observed for the old sample compared to new one.