Low dynamic power integrated circuits design using reliable cell-downsizing methodology

The continuous reduction of feature size and increase in chip density have made power becomes an important design parameter in today´s deep submicron digital designs. Conversely, design engineers perform power estimation and optimization at every design stage to improve the performance and productivity of the design. During most synthesis process, synthesis tools prefer to use larger gates in the design to avoid timing violation. However, larger cells imply increasing in design area and power dissipation. Over sizing the cells in design is a waste in term of resources. Hence, this research introduces an effective and reliable design automation for cell-downsizing methodology in cell-based design. The proposed methodology is a discrete sizing methodology that assumes the gate size is a discrete variable. The cell-downsizing methodology is a constraint optimization. The methodology is tested using a 22nm industry design and the experiment result shows the significant improvement of dynamic power dissipation up to 36.29%.