Analog layout design optimization and verification for SoC

This paper introduces a complete methodology for analogue layout design using a concept of cells and arrays for analog layout generation, migration and reuse. With careful integration of the device sizes and layout generation tasks, a fully functional layout designs are able to be generated in a few steps and fraction of time. This paper describes such a system and shows its importance in obtaining a layout that can be configurable like a set of building blocks that meets all design specifications.