DocumentCode :
2432718
Title :
Determination of sensitive inputs of nanoscale digital circuits using Bayesian network analysis
Author :
Khalid, Usman ; Anwer, Jahanzeb ; Singh, Narinderjit ; Hamid, Nor H. ; Asirvadam, Vijanth S.
Author_Institution :
Electr. & Electron. Eng. Dept., Univ. Teknol. PETRONAS (UTP), Bandar Seri Iskandar, Malaysia
fYear :
2011
fDate :
28-30 Sept. 2011
Firstpage :
186
Lastpage :
189
Abstract :
The reliability of digital circuits is greatly distorted as the VLSI design cycle enters into nanoscale arena. In the past, the inputs of digital circuits were considered deterministic but shifting of transistor technology into nanoscale dimensions has made their behaviour totally probabilistic. The reason is that logic level voltages suffer from a number of fluctuations due to the effect of signal noise and transient faults. These inputs are now considered as distributed inputs and there is a need to model them probabilistically. This paper shows how to model these inputs and their effects on digital circuits´ reliability. For the analysis covered in this paper, we will determine sensitive inputs of few test circuits followed by their justification and anticipated effects.
Keywords :
Bayes methods; VLSI; integrated circuit design; integrated circuit reliability; probability; Bayesian network analysis; VLSI design; digital circuit reliability; distributed inputs; logic level voltages; nanoscale arena; nanoscale digital circuits; sensitive inputs; signal noise; transient faults; transistor technology; Adders; Digital circuits; Integrated circuit modeling; Integrated circuit reliability; Nanoscale devices; Probabilistic logic; Bayesian networks; Probabilistic digital input; Reliability; Sensitive inputs;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Micro and Nanoelectronics (RSM), 2011 IEEE Regional Symposium on
Conference_Location :
Kota Kinabalu
Print_ISBN :
978-1-61284-844-0
Type :
conf
DOI :
10.1109/RSM.2011.6088320
Filename :
6088320
Link To Document :
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