Modeling and performance evaluation of RISC/B processor

Author

Yang-Yuch Chen ; Yang, Ted C.

Author_Institution

Grad. Inst. of Appl. Math., Nat. Chung Hsing Univ., Taichung, Taiwan

fYear

1990

fDate

23-26 Apr 1990

Firstpage

63

Lastpage

73

Abstract

Consideration is given to the performance analysis of a RISC (reduced instruction set computer) machine (RISC/B) based on timed Petri net (TPN) models. The operation flow graph is created according to the RISC/B instruction execution patterns and the pipeline structures. A TPN is used to model the operation in the graph. A sequence of discrete-time Markov chains (DTMCs) is built from the TPN in the instruction execution path. The DTMC model is useful for the study of various design and analysis issues in processor architecture. The model has been validated by comparing the analytical results with those obtained from the RISC/B prototype machine. Bottlenecks in the prototype have been identified through the model and cache performance tradeoffs have been investigated from both the architectural and the organizational viewpoints

Keywords

Markov processes; Petri nets; reduced instruction set computing; DTMC model; RISC/B instruction execution patterns; RISC/B processor; RISC/B prototype machine; cache performance tradeoffs; discrete-time Markov chains; instruction execution path; operation flow graph; organizational viewpoints; performance analysis; performance evaluation; pipeline structures; processor architecture; reduced instruction set computer; timed Petri net; Arithmetic; Character generation; Computer aided instruction; Counting circuits; Logic; Memory management; Radio frequency; Reduced instruction set computing; Registers; Strontium;

fLanguage

English

Publisher

ieee

Conference_Titel

Systems Integration, 1990. Systems Integration '90., Proceedings of the First International Conference on

Conference_Location

Morristown, NJ

Print_ISBN

0-8186-9027-5

Type

conf

DOI

10.1109/ICSI.1990.138663

Filename

138663