DocumentCode :
2432846
Title :
A memory-efficient architecture for low latency Viterbi decoders
Author :
Tang, Yun-Ching ; Hu, Do-Chen ; Wei, Weiyi ; Lin, Wen-Chung ; Lin, Hongchin
fYear :
2009
fDate :
28-30 April 2009
Firstpage :
335
Lastpage :
338
Abstract :
A memory-efficient Viterbi decoder (VD) named modified state exchange (MSE) is proposed using pre-trace back technique to obtain the decoded data by blocks. Since the architecture of MSE can record the ldquosurvival state number,rdquo which can also be the resulted decoded data, no decision bit is required during trace back and decoding. Therefore, the power and chip area of the survivor memory unit in the MSE method are smaller than those of the existing trace back approaches. The VD using MSE approach for (2, 1, 6) convolutional code was designed using TSMC 0.18 mum 1P6M CMOS technology. The core area is 0.69 mm2 with power consumption of 58 mW at 100 MHz.
Keywords :
CMOS integrated circuits; Viterbi decoding; convolutional codes; memory architecture; CMOS technology; convolutional code; low latency Viterbi decoders; memory-efficient architecture; modified state exchange; pretrace back technique; survival state number; AWGN; CMOS technology; Clocks; Convolutional codes; Delay; Energy consumption; Maximum likelihood decoding; Memory architecture; Registers; Viterbi algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, Automation and Test, 2009. VLSI-DAT '09. International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4244-2781-9
Electronic_ISBN :
978-1-4244-2782-6
Type :
conf
DOI :
10.1109/VDAT.2009.5158163
Filename :
5158163
Link To Document :
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