Modeling of the reliability baseline for process control monitoring kerf structures

We present the Product Chip Monitor-Wafer Level Reliability (PCM-WLR) model and characteristic of a 45nm thick gate-oxide (GOX), trench DMOS technology. The process control monitor (PCM) refers to the suite of test structures usually placed in the scribe line (alternatively named kerf, street or test key) separating product die on the wafer. The motivation of this work is to establish the baseline of the dielectric and device reliability for the kerf PCM structure that will enhance the capability to perform lot disposition in the event of PCM test out-of-control (OOC). Different test structures will be stressed and correlation study is performed with existing models. The experiment was performed at Infineon Technologies Kulim Failure Analysis Lab and that test wafers were fabricated by Infineon Technologies.