Incremental physical design method for flat SOC design

SOC designs for consumer electronics often evolve generation by generation in a very short time. Besides the needs for merging more functionality, more and more enhancements are for the purpose of interface upgrading for new standards and better or faster signal processing hardware engines for video/audio encoding and decoding. Physical designs for these kinds of enhanced chips can reuse large potions of the previous layout and do not need to be re-implemented from the ground up to shorten the time to market. However, traditional physical incremental design method is becoming impractical, especially for the flat design, which usually can has the advantage of the smaller die size compared with the hierarchical design. In this paper, we propose an incremental physical design method to take the advantages of the hieratical design while maintaining the cost strength in the flat design. Our proposed method has been successfully applied to our next generation multimedia chip and the results show that no design iteration is needed and the run time is at least 5 times faster compared with the traditional method.