Fully On chip area efficient LDO voltage regulator

Author

Suresh, A. ; Patri, Sreehari Rao ; Dwibedy, Debasish ; Bhat, Sunilkumar ; Gaurav, K. ; Krishnaprasad, K.S.R.

Author_Institution

Dept. of Electron. & Commun. Eng, Nat. Inst. of Technol. Warangal, Telangana, India

fYear

2014

fDate

22-25 Oct. 2014

Firstpage

1

Lastpage

5

Abstract

A novel full on-chip, area efficient low dropout linear regulator is presented in this paper. This LDO is designed with a recycling folded cascode error amplifier that offers very good stability and a load regulation of 6.760μV/mA. A refined frequency compensation scheme is used which maintains LDO stability over entire load current range i.e. 0-100mA and fast transient response without any necessity of output capacitor. The overshoot/undershoot in the output voltage under the extreme load transients are 195.3mV /71.7mV. The area of the presented LDO is greatly reduced due to removal of on-chip high output capacitance. The area of presented LDO is only 0.05 mm². The LDO presented requires a bias current of 70μA and 200mV dropout voltage and is designed in 180nm technology.

Keywords

amplifiers; circuit stability; integrated circuit design; transient response; voltage regulators; LDO stability; LDO voltage regulator; current 0 mA to 100 mA; dropout voltage; folded cascode error amplifier; frequency compensation scheme; load regulation; load transients; low dropout linear regulator; size 0.05 mm; size 180 nm; transient response; voltage 195.3 mV; voltage 200 mV; voltage 71.7 mV; Capacitors; Recycling; Regulators; System-on-chip; Transient response; Transistors; Voltage control; High slew rate; low-dropout regulator; low-quiescent current; recycling folded cascode error amplifier;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON 2014 - 2014 IEEE Region 10 Conference

Conference_Location

Bangkok

ISSN

2159-3442

Print_ISBN

978-1-4799-4076-9

Type

conf

DOI

10.1109/TENCON.2014.7022464

Filename

7022464