Development and simulation of PIE encoder architecture for UHF RFID reader based on FPGA

Author

Ibrahim, A. ; Ismail, I. ; Abdullah, A.T.

Author_Institution

Fac. of Electr. Eng., Univ. Teknol. MARA, Shah Alam, Malaysia

fYear

2012

fDate

7-8 April 2012

Firstpage

58

Lastpage

63

Abstract

The paper outline development and simulation of Pulse Interval Encoding (PIE) encoder architecture for Ultra High Frequency (UHF) Radio Frequency Identification (RFID) reader based on Field Programmable Gate Array (FPGA). The PIE encoder architecture presented in this paper is according to International Organization for Standardization and International Electrotechnical Commission (ISO/IEC 18000-6) protocol. The behavior of the PIE encoder architecture is realized by derivation of Verilog Hardware Description Language (HDL) code in Quartus II software. Utilizing the ModelSim-Altera, the PIE encoder architecture is simulated to observe its functionality. The designing of the encoder is intended for uses in UHF RFID passive interrogator.

Keywords

encoding; field programmable gate arrays; hardware description languages; radiofrequency identification; FPGA; ISO-IEC; International Electrotechnical Commission; International Organization for Standardization; ModelSim-Altera; PIE encoder architecture; Quartus II software; UHF RFID passive interrogator; UHF RFID reader; VHDL code; Verilog hardware description language code; field programmable gate array; pulse interval encoding encoder; ultrahigh frequency radiofrequency identification reader; Computer architecture; Encoding; Hardware design languages; IEC standards; ISO standards; Protocols; Radiofrequency identification; FPGA; RFID; UHF READER;

fLanguage

English

Publisher

ieee

Conference_Titel

Business Engineering and Industrial Applications Colloquium (BEIAC), 2012 IEEE

Conference_Location

Kuala Lumpur

Print_ISBN

978-1-4673-0425-2

Type

conf

DOI

10.1109/BEIAC.2012.6226106

Filename

6226106