MIMO Accelerator: A design flow for a programmable MIMO decoder architecture

We present a complete design flow for a novel programmable MIMO decoding architecture. The architecture uses a reconfigurable vector-coarse processing core with integrated dynamic scaling, combined with a novel memory access scheme that utilizes properties of matrix processing to afford both flexibility and single cycle access to vector operands. The architecture delivers DSP-like programmability while delivering PDP (power-delay-product) and area/energy efficiency that is three orders of magnitude higher than a DSP and on the same order of magnitude as dedicated ASIC designs. The hardware architecture is user reconfigurable; allowing independent control over the structure, word length, size of the processor, vector dimensions, and flexible memory access . The hardware configuration process is aided through a tool flow that feeds back real-time information on expected resources and performance, as well as allowing the automatic generation of hardware configurations from a target program. The design cycle of MIMO decoders is accelerated through both the architecture, which allows programmability approaching DSP and performance approaching dedicated hardware, and the hardware configuration flow which allows rapid analysis of hardware design tradeoffs.