Title :
LDPC-based advanced FEC for 100 Gbps transmission
Author :
Mizuochi, Takashi ; Miyata, Yoshikuni
Author_Institution :
Inf. Technol. R&D Center, Mitsubishi Electr. Corp., Kamakura
Abstract :
Practical FEC implementation of 100 Gbps long-haul transmission is discussed. An LDPC code using a novel algorithm is introduced to reduce circuit complexity. Simulation shows that the Q limit is 7.1 dB, and that the concatenation effectively suppresses unwanted error-floor.
Keywords :
forward error correction; parity check codes; FEC; LDPC; Bit error rate; Circuits; Complexity theory; Digital signal processing; Error correction; Forward error correction; Large scale integration; Optical receivers; Parity check codes; Redundancy;
Conference_Titel :
IEEE/LEOS Summer Topical Meetings, 2008 Digest of the
Conference_Location :
Acapulco
Print_ISBN :
978-1-4244-1925-8
Electronic_ISBN :
1099-4742
DOI :
10.1109/LEOSST.2008.4590567
